1. Field of the Invention
The present invention generally relates to nanotechnology, nanoelectronics, semiconducting polymer electronics, and to printed electronics at the nanometer, micrometer, and millimeter scale, and in particular, to circuits created from carbon nanotubes, graphene nanoribbons, strips of semiconducting polymers, and semiconducting inks used in printed electronics.
2. Background of the Invention
Even in isolation, nanoelectronics is an area of great unrealized commercial promise. This is driven by a number of factors, including the needs for every greater circuit densities and every-greater operating speeds. Additionally, there is at least one other important driver in that nanoelectronics will eventually be required for interfacing with various types of other nanosystem elements such as nanoscale sensors and actuators.
In particular within the area of nanoelectronics, active electronic semiconducting components realized with carbon nanotubes or graphene nanoribbons have attracted attention. Both carbon nanotubes and graphene nanoribbons are nanoscale forms of carbon, and some earlier taxonomies regard nanotubes as a type of graphene. More recently these materials, both allotropes of carbon, have come to be collectively referred to as “nanocarbon.” In 2008 Andre Geim and team proved graphene sheets represent the fastest known semiconducting material, with a mobility greater than 200,000 cm2/Vs at room temperature (more than 100 times greater than the mobility of silicon, at least 30 times greater than the mobility of gallium-arsenide, and greater than the mobility of carbon nanotubes),
P-type and N-type field-effect transistors have been demonstrated both theoretically and experimentally using carbon nanotubes, with additional noteworthy developments in carbon nanotube-based junction transistors, tunneling transistors, ballistic/near-ballistic field-effect transistors, single-electron transistors, field emission nanotriodes, resistors, diodes, light-emitting devices, photo-responsive devices, etc. Citations for these may be found in co-pending U.S. patent applications U.S. Ser. No. 12/025,562 and U.S. Ser. No. 12/033,212, and therein in particular provided discussions, citations, and teachings regarding carbon nanotube field effect transistors (CNFETs). Further, inspired by exciting research results for CNFET and startling discoveries regarding graphene sheets and ribbons, subsequent effort has been directed to creating graphene nanoribbon field effect transistors (GRFETs or GFETs) employing similar geometric electrode structures as employed in CNFETs.
Further, the area of printed electronics (i.e., the “printing” of interconnected circuit elements from various types of semiconducting, conducting, resistive, and insulating inks) has recently begun developing realistic printed electronics techniques at the nanometer scale in addition to traditional millimeter and micrometer scales (see for example, ObservatoryNano, ICT Sector Focus Report: Printed Electronics, April 2010, available at http://www.observatorynano.eu/project/filesystem/files/ObservatoryNanoFocusReport PrintedElectronics.pdf).
Despite these promising advancements, there are at least five problems holding back the development of systems comprising nanoelectronics for commercial applications:                The lack of viable analog capabilities for interfacing nanosensors and nanoactuators with “outside world” and nanosystem-internal digital nanoelectronics (for example, in the 2006 IBM nanotransistor ring oscillator reported in “An Integrated Logic Circuit Assembled on a Single Carbon Nanotube,” Z. Chen et al., Science, Mar. 24, 2006, Vol 311, pp. 1735, the output signal from the nanotransistor ring oscillator suffered extensive signal level losses as it was brought into the larger-scale world by direct connection to a 50-ohm input of spectrum analyzer);        The nanocircuit component placement problem for moderate to large numbers of nanotransistors;        The nanocircuit internal interconnection problem for moderate to large numbers of nanotransistors;        The techniques for designing and layout of carbon nanotube circuits are typically not developed in such a way as to be extendable to other types of nanotransistors and molecular transistors;        Even low-level prototyping of carbon nanotube nanotransistor circuits is difficult and expensive.        
Many aspects of these five problems are addressed in the present and by related co-pending patent applications U.S. Ser. No. 12/025,562 with priority date Feb. 5, 2007, U.S. Ser. No. 12/033,212 with priority date Feb. 17, 2007, and U.S. 61/348,366 with a priority date of May 26, 2010.
More specifically, in order to interface with the all-important “outside world” basic analog capabilities such as differential amplifiers, operational amplifiers, comparators, digital-to-analog converters are required. Similarly, in order to interface with proposed nanosystem-internal digital nanoelectronics, there is also similar need for basic analog capabilities such as differential amplifiers, operational amplifiers, comparators, digital-to-analog converters. Although field-emission nanotriode differential amplifiers comprising carbon nanotube emission elements have been modeled and demonstrated, these devices are larger in physical scale than companion nanoelectronic components, require complex fabrication, and appear difficult to integrate with other types of nanoelectronic components. The absence of basic compatible analog capabilities in nanoelectronics has been a key missing link in nanoelectronics and nanosystem technologies.
Additionally, there is an internal interconnection and a component placement problem for nanocircuits comprising moderate to large numbers of nanotransistors. In order to create non-repetitive systems of adequate complexity, tens to hundreds to thousands of nano-transistors must be individually placed and uniquely interconnected. To fabricate carbon nanotube or graphene ribbon nanocircuits comprising a moderate to large numbers of transistors, it would appear that large numbers of individual carbon nanotubes or electrically-isolated regions of graphene must be separately manipulated or somehow grown in proper locations, and somehow interconnected.
As mentioned, co-pending patent applications U.S. Ser. No. 12/025,562, U.S. Ser. No. 12/033,212, and U.S. 61/348,366 contribute to addressing each of these problems. Some of the aspects of these inventions include:                Exemplary techniques for creating entire essential multitransistor analog transistor circuits (such as entire differential amplifiers and comparators) from a small portion of a single semiconducting nanoscale object (such as a carbon nanotube, graphene-ribbon, etc.) using contemporary high-resolution photolithography, metallization, and doping manufacturing used in the silicon industry;        Exemplary techniques for adapting a complete multi-transistor single carbon-nanotube/graphene-ribbon differential amplifier so that portions within it and/or other regions of the same nanotube/ribbon can be used to directly integrate a wide variety of sensors within the signal amplifier, improving sensitivity and high-frequency performance;        Exemplary fabrication can involve:                    creating one or more interconnection layers;            draping or otherwise positioning a physically-linear-structure semiconducting material (nanotubes, ribbons, etc.) over a robust range of target electrodes;            any differential doping (vi photolithographic resist, focused implantation, etc.) required to create any complementary transistor types.                        
However, there are additional problems of concern that provide barriers to commercialization of nanoelectronics.
One of these additional problems is that the techniques for designing and layout of carbon nanotube circuits are not extendable to other types of nanotransistors and molecular transistors. The specialized physics, models, and many of the above limitations appear to preclude much re-use of the models and techniques with other types of nanotransistors and molecular transistors, making R&D funding opportunities more rarefied and elite.
Another of these additional problems is that the aforementioned specialized physics, models, and many of the above limitations make it difficult for broader populations of circuit designers to conceive of meaningful circuits and systems they could design.
Yet another of these additional problems is that prototyping of nanoelectronic circuits in general can be very difficult, time consuming, and expensive. The specialized physics, models, and many of the above limitations tend to isolate numerical simulation models to a precious few specialists and specialized isolated software programs. Further, the aforementioned fabrications costs and design barriers make physical prototyping out of reach for even most of the privileged few of the precious few specialists with access to the aforementioned rarefied and elite R&D funding opportunities.
The present invention addresses these three additional problems with (1) methods and (2) software-based systems for executing on one or more computers. These methods and software-based systems leverage one or more of:                Use of field effect transistors that can be readily fabricated from placement of an insulated conductor proximate to the strip, tube, or ribbon of semiconducting material arranged to span the distance between two contacting electrodes;        Use of a class of circuit topologies (“chain/leapfrog”) that is applicable to implementing multi-transistor circuits on elongated strips, tubes, or fibers of semiconducting material;        Use of additional circuit design approaches, methods, and/or arrangements for obtaining chain/leapfrog circuit topologies that terminate on either end in one of one or more types of power supply terminals;        Use of a chain/leapfrog circuits library comprising designs for a plurality of chain/leapfrog circuit modules; and        Providing support for “IP cores,” “System-on-a-nanotube,” and other related modular design approaches as taught in co-pending U.S. patent applications U.S. Ser. No. 12/025,562 with a priority date of Feb. 5, 2007, U.S. Ser. No. 12/033,212 with a priority date of Feb. 17, 2007, and U.S. 61/348,366 with a priority date of May 26, 2010.The invention provides for conducting, insulating, semiconducting, and other types of printed electronic “inks” to used in a chain/leapfrog printable electronics realization. The invention also provides for these inks to be chosen so as to match or nearly approximate aspects of the electrical behavior and operative device structures of a direct emulation target such as chain/leapfrog carbon nanotube electronics, chain/leapfrog graphene ribbon electronics, and nanoscale chain/leapfrog semiconducting polymers. The invention further provides for these inks and subordinate structures used in the extensions to printable electronics to serve as scaled-up physical prototypes that can be interpreted through computer software so as to compensate for scale and/or minor differences. Yet further, the invention provides for the inks and subordinate structures used in the extensions to printable electronics to be adapted and combined with printable or other substrate structures to serve as scaled-up physical prototypes that can be interpreted through computer software so as to numerical impose additional effects that cannot be directly emulated.        